Stand aside, dual-core and quad-core chips. A Silicon Valley startup has released the world's first 64-core chip, and is already planning for a 120-core version.
Silicon Valley-based Tilera on Monday announced its Tile64 processor, which the company described as the first in a series of Tile processors "based on a revolutionary architecture that can scale to hundreds and even thousands of cores."
Tilera said that each core is full-featured, programmable, and capable of running Linux. The chip offers 10 times the performance-per-watt of Intel's dual-core Xenon, according to the company, and 40 times the performance of Texas Instruments' leading digital signal processor.
Calling the Tile64 "the first significant new development in chip architecture in a decade," Tilera President and CEO Devesh Garg said in a statement that "existing multicore technologies simply cannot scale beyond a handful of cores." But Tile64's "revolutionary" platform, he added, solves the challenges of multicore scalability.
Outgrowth of MIT Research
Gartner analyst Martin Reynolds said the biggest challenge now for such massively multicore chips is "programming to handle all the different processing threads." He added that, while such processing is currently targeted at specialized applications, the average business or consumer user might eventually use such chips for processing-intensive tasks such as high-end multimedia compression or decompression.
Some of those specialized applications likely will be in advanced networking and digital multimedia products. Tilera, founded in 1994 to commercialize the multicore research of MIT's Dr. Anant Agarwal, said it already has a dozen customers and more than 40 patents. Agarwal's research on a mesh-based architecture was supported by funding from the Defense Advanced Research Projects Agency and the National Science Foundation.
The research led Tilera to release a prototype of its first tiled multicore processor and related in 2002. The Santa Clara, California-based company said the performance advantage for its tiled multicore chips is due to the elimination of the on-chip bus interconnect through which information flows between cores or between the chip and outside components.
The iMesh Architecture
Like a circle in a growing city, current bus architecture can lead to an information traffic jam as more cores are added. But Tilera said it eliminates this congestion by providing a communications switch on each processor and assembling them in a grid on the chip, essentially creating a two-dimensional traffic system that avoids centralization.
This iMesh architecture -- with "i" standing for intelligent -- provides a bandwidth that the company said is orders of magnitude greater than a conventional bus, with shorter distances for data to travel between chips. It allows for processing grids that can be scaled as the requires, using relatively low power.
The company said that each of the 64 cores on the new Tile64 processor not only is capable of running its own operating system, but also is a full-featured, general-purpose processor that includes L1 and L2 caches, as well as a distributed L3 cache.
The Tile64 processor is available now in three different device variants based on frequency. Production pricing for the Tile64 family starts at $435 in 10,000-unit quantities. The 64-core chip is only the first stop in Tilera's roadmap for massive configurations. In addition to a 120-core version, a 36-core processor is planned.